This invention relates to a digital-to-analog (D/A) converter of the current cell type comprising a plurality of current mirrors and selecting means therefor. More particularly, this invention relates to such a D/A converter formed by taking into consideration the effects of parasitic resistances of conductive lines through which power is supplied to the current mirrors.
FIG. 6A shows, for illustration, the circuit structure of a prior art D/A converter of the current cell type having six current mirrors, or six pairs of transistors Tr0+Tr1, Tr0+Tr2, Tr0+Tr3, Tr0+Tr4, Tr0+Tr5 and Tr0+Tr6, and a decoder (selecting means) 3 for decoding a digital input D and generating and outputting selection signals to the current mirrors. As an analog output A is generated corresponding to the digital input D by totaling output currents from those of the transistors Tr1-Tr6 selected by the selection signals, output currents i1-i6 of the plurality of current mirrors are selected to form the analog output A according to the digital input D.
Explained more in detail, transistor Tr0 is a MOS transistor on the input side of the current mirrors, its drain being connected to a power source line 1, its source being connected to a constant current source 2 for a reference current i0 and its gate being connected to the gates of the transistors Tr1-Tr6. In other words, transistor Tr0 serves as an input transistor for providing a constant reference current.
Transistor Tr1 is a MOS transistor on the output side of one of the current mirrors. Its drain is connected to the power source line 1, and its source, through which mirror current i1 flows, is connected through a switch SW1 to an output line for the analog output A. Transistor Tr2, too, is a MOS transistor on the output side of a current mirror, its drain being connected to the power source line 1 and its source, through which mirror current i2 flows, being connected through another switch SW2 to the output line for the analog output A. The other transistors Tr3-Tr6 may be similarly described, each being a MOS transistor on the output side of a corresponding current mirror, the drain of each being connected to the power source line 1 and the source of each being connected through a corresponding one of switches SW3-SW6 to the output line for the analog output A and having a corresponding mirror current i3, i4, i5 or i6 to flow therethrough. In summary, transistors Tr1-Tr6 are all transistors on the output side, having the same transistor (Tr0) in common on the input side. The aforementioned plurality of pairs of transistors Tr0+Tr1, Tr0+Tr2, Tr0+Tr3, Tr0+Tr4, Tr0+Tr5 and Tr0+Tr6 form a partially overlapping plurality of current mirrors, and their output currents i1-i6 may or may not be included in the analog output A, depending on whether the corresponding switches SW1-SW6 are in the conductive or closed (ON) condition or in the cut-off or open (OFF) condition.
The decoder 3 serves to switch on by simple means a suitable number of the switches SW1-SW6 corresponding to the digital input D while the selection signals to the current mirrors, or their ON and OFF conditions, are controlled. As the value of the digital input D increases from "0" sequentially to "1", "2", "3", "4", "5" and "6", for example, the decoder 3 switches on switches SW1, SW2, SW3, SW4, SW5 and SW6 from OFF to ON positions at each of the corresponding points in time. Similarly, when the value of the digital input D decreases, these switches are switched off from the ON to OFF positions in the reverse order. In other words, the decoder 3 usually selects the output transistors in the order of their proximity to the input transistor Tr0 when the digital input D increases (and in the reverse order when the digital input D decreases).
If each current mirror of such a D/A converter functioned ideally, the currents i1-i6 would be all equal, and the current values i1, i1+i2, i1+i2+i3, . . . , i1+i2+i3+i4+i5+i6 of the analog output A corresponding to the values of digital input D "0", "1", "2", . . . "6" would form a step function curve with equal steps, as shown by two-dot dashed line in FIG. 6B. In the case of a D/A converter of a similar structure with an increased number of current mirrors corresponding to an increased number of bits for the digital input D, the input-output curve would become a straight line with a constant slope, as shown by a two-dot dashed line in FIG. 6C.
In reality, however, the power source line 1 has parasitic resistance and the current which flows therethrough is fairly large. Thus, unless the resistance of the power source line 1 can be reduced to a negligible level, the conversion characteristic of the D/A converter is significantly different from the ideal situation described above.
What is herein referred to as the power source line 1 actually includes not only the line from the power supply terminal of the source voltage Vdd to the transistor Tr0 on the input side but also the first branch line branching therefrom and reaching the first transistor Tr1, the second branch line branching from the first branch line and reaching the second transistor Tr2, and so on to the last branch line branching from the penultimate branch line and reaching the last transistor Tr6. In other words, resistances Ra-Rf and R0-R6 are parasitically distributed among the lead lines as shown in FIG. 6A such that the currents i1-i6 are not all equal but tend to sequentially decrease, or i1&gt;i2&gt;i3&gt;i4&gt;i5&gt;i6. As a result, the input-output characteristic of such a D/A converter is usually a step function curve with unequal steps (as shown by a solid line in FIG. 6B). In the case of such a D/A converter with an increased number of bits for the digital input D, the deviation from the ideal situation becomes greater as the value increases as shown by a solid line in FIG. 6C.
Japanese Patent Publication Tokkai 7-154260 disclosed a method of counteracting such ill effects of parasitic resistances in conductive lines. According to this technology, the power source terminal and each conductive line are duplicated such that the output currents from the individual current mirrors can be uniformized and a layout is made such that the sums of the lengths of the paths will become equal.
This method, however, cannot solve the problem for all cases because there are situations wherein it is difficult to duplicate the power source terminal or the conductive lines. There may also be situations wherein, although such duplication is not impossible to carry out, it is still not desirable to increase the number of power source terminals or the area for the wiring or the layout of the wiring may be difficult. Thus, it is not desirable to resort to such a conventional duplication method just in order to counteract the ill-effects of parasitic resistances of the conductive lines on the conversion characteristic.
For D/A converters to be mounted to an LSI circuit, limitations on the design become severer regarding the number of terminals, the area for the wiring and the layout as a whole because LSI circuits are requires to be miniaturized and highly integrated.